Intel Agilex: 10nm FPGAs with PCIe 5.0, DDR5, and CXL

Wednesday, April 3rd, 2019 - FPGAs, Teknologi

Intel Agilex: 10nm FPGAs with PCIe 5.0, DDR5, and CXL

Ever since Intel purchased Altera for an enormous amount of money a few years ago (ed: $16.7B), the FPGA portfolio that has been coming out has largely been a product of the pre-Intel days. Today however that changes, as Intel is announcing its first fully Intel-designed FPGA, built upon its own internal 10nm process, with the Agilex brand name. This new range of products is set to roll out later this year for sampling, and offer a mix of analog, digital, memory, custom IO, and eASIC variations within a singular platform.


For users familiar with Intel’s FPGA family, the new Agilex portfolio is a generational upgrade over the current Stratix 10 family. The new Agilex parts, according to Intel, offer up to 40% higher performance or 40% lower power, up to 40 TFLOPs of DSP performance, and support for all the latest and future technologies. It’s this latter part that becomes important as the role of the FPGA is transmogrifying into a general purpose design platform into an optimized compute platform.

The Agilex FPGA builds on similar design principles to the Stratix – a centralized FPGA block of gates with hardened features and external connections out to several different technologies, based on the customer requirements. For these external connections, Intel is using its Embedded Multi-Die Interconnect Bridge (EMIB) technology, which in the examples given can be expanded into other chiplets. Some of the chiplet suggestions from Intel include High Bandwidth Memory (HBM), next-generation 112G transceivers, PCIe Gen 5.0 root complexes, Compute eXpress Link interfaces (through PCIe 5.0), additional CPU cache coherent interconnects, and other chiplets/IP as determined by the customer. To add into all of this, Agilex will also support Intel’s Optane DC Persistent Memory.

One of the big updates to the FPGA family comes through Intel’s recent acquisition of eASIC. Intel has actually been working with eASIC for several years, however in 2018 it purchased the company outright to deliver additional synergies into its programmable product portfolio. With Agilex, the first stage of this vision is set to be delivered – customers that want quick IP deployment can choose to work with Intel’s eASIC division for chiplet IP deployment or fusion into the FPGA, quicker than the customer is able to do themselves, and taking advantage of Intel’s own product design chain.

The use of PCIe Gen 5.0 is also a big element to Agilex, as it allows customers to connect directly with future PCIe 5.0 host devices, but it also allows for Intel’s new Compute eXpress Link technology, which builds upon the PCIe 5.0 physical standards. CXL is Intel’s own cache coherent connect, set to work alongside (or compete, depending on who you ask) with GenZ and CCIX. Given Intel’s comments on CXL, it’s clear that when PCIe 5.0 is ubiquitous, it intends to bring its add-in card portfolio to run either on CXL, PCIe 5.0, or both. And one of Intel’s big topics recently is its movement into discrete graphics, which could take advantage of this. It would appear however that Agilex may be the first to take advantage of Intel’s new standard when it’s ready – until that point, Intel states that Agilex will support UPI as its main cache coherent connectivity option.

As always with the FPGA market, Intel is targeting the usual suspects that might use them: networking, cloud, embedded, and enterprise. The newest use cases for FPGAs in this field are related to edge deployments as well as networking, so we can expect to see Intel’s case studies of the new hardware in these areas.  AI is also important, with Intel keen to announce that its Agilex portfolio will have hardened support for bfloat16 and other low precision number formats, even down to INT2. These will be managed through Intel’s OneAPI strategy, and the company states that even though the FPGA can be used for AI, it is set to work alongside Nirvana and Movidius, rather than compete.

One element that was interesting during our discussions with Intel about Agilex is that the company mentioned 3D stacking and integration. I quizzed if this was just a mentioning of HBM, or something more detailed such as the Foveros technology that the company demonstrated at the end of 2018. Intel stated that the 3D integration is going to be an expected evolution of the product line, and a view to the future with its second generation of Agilex. Perhaps expected, no date about when this would happen was forthcoming, but interesting nonetheless.

Agilex will come in three flavors: F, I, and M, with exact support listed below. The Intel Quartus Prime software will support these variants from April 2019, and first device availability of the F-series will be from Q3 2019.

Gallery: Intel Agilex

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