TSMC: First 7nm EUV Chips Taped Out, 5nm Risk Production in Q2 2019

Tuesday, October 9th, 2018 - Semiconductors, Teknologi

TSMC: First 7nm EUV Chips Taped Out, 5nm Risk Production in Q2 2019

Last week, TSMC made two important announcements concerning its progress with extreme ultraviolet lithography (EUVL). First up, the company has successfully taped out its first customer chip using its second-generation 7 nm process technology, which incorporates limited EUVL usage. Secondly, TSMC disclosed plans to start risk production of 5 nm devices in April.

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First 7 nm EUV Chip Tapes Out at TSMC

TSMC initiated high-volume manufacturing of chips using its first generation 7 nm fabrication process (CLN7FF, N7) in April. N7 is based around deep ultraviolet (DUV) lithography with ArF excimer lasers. By contrast, TSMC’s second-generation 7 nm manufacturing technology (CLN7FF+, N7+) will use extreme ultraviolet lithography for four non-critical layers, mostly in a bid to speed up production and learn how to use ASML’s Twinscan NXE step-and-scan systems for HVM. Factual information on the improvements from N7 to N7+ are rather limited: the new tech will offer a 20% higher transistor density (because of tighter metal pitch) and ~8% lower power consumption at the same complexity and frequency (between 6% and 12% to be more precise).

While the advantages of N7+ over its predecessors are not significant (e.g., TSMC has never mentioned performance increases that the new tech is expected to bring), it will still almost certainly be embraced wholeheartedly by developers of mobile SoCs who need to release new chips every year. That said, it is not surprising that TSMC has already taped out the first chip using its N7+ technology. Furthermore, the company is prepping a specialized version of the process aimed at the automotive industry, which indicates that N7+ is going to be a “long” node.

TSMC is not disclosing the name of the customer whose N7+ SoC it has taped out, but considering the foundry’s alpha customers for new process technologies in the recent years, the leading suspects are obvious.

Advertised PPA Improvements of New Process Technologies
Data announced by companies during conference calls, press briefings and in press releases
 TSMC
16FF+
vs
20SOC
10FF
vs
16FF+
7FF
vs
16FF+
7FF
vs
10FF
7FF+
vs
7FF
5FF
vs
7FF
Power60%40%60%<40%10%20%
Performance40%20%30%?same (?)15%
Area Reductionnone>50%70%>37%~17%45%

5 nm on Track

After N7+ comes TSMC’s first-generation 5 nm (CLN5FF, N5) process, which will use EUV on up to 14 layers. This will enable tangible improvements in terms of density, but will require TSMC to extensively use EUV equipment. When compared to TSMC’s N7, N5 technology will enable TSMC's customers to shrink area of their designs by ~45% (i.e. transistor density of N5 is ~1.8x higher than that of N7), increase frequency by 15% (at the same complexity and power) or reduce power consumption by 20% power reduction (at the same frequency and complexity).

TSMC will be ready to start risk production of chips using its N5 tech in April, 2019. Keeping in mind that it typically takes foundries and their customers about a year to get from risk production to HVM, it seems like TSMC is on-track for mass production of 5 nm chips in Q2 2020, right in time to address smartphones due in the second half of 2020.

EDA tools for the N5 node will be ready in November, so chip designs may be well underway now. But while many foundation IP blocks for N5 are ready today, there are important missing pieces, such as PCIe Gen 4 and USB 3.1 PHYs, which may not be ready until June. For some of TSMC's clients the lack of these pieces is not a problem, but many will have to wait.

One of the factors that prevents smaller companies from designing FinFET chips is development cost. Some estimates put the average cost to develop an SoC at around $150 million in labor and IP licenses. With N5 generation, these expenditures will rise to $0 – $250 million, according to EETAsia, which will limit the number of parties interested in using the tech.

Related Reading:

Source: EETAsia

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