TSMC’s 5nm EUV Making Progress: PDK, DRM, EDA Tools, 3rd Party IP Ready

Friday, April 5th, 2019 - Semiconductors, Teknologi

TSMC’s 5nm EUV Making Progress: PDK, DRM, EDA Tools, 3rd Party IP Ready

TSMC this week said that it has completed development of tools required for design of SoCs that are made using its 5 nm (CLN5FF, N5) fabrication technology. The company indicated that some of its alpha customers (which use pre-production tools and custom designs) had already started risk production of their chips using its N5 manufacturing process, which essentially means that the technology is on-track for high-volume manufacturing (HVM) in 2020.

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TSMC’s N5 is the company’s 2nd generation fabrication technology that uses both deep ultraviolet (DUV) as well as extreme ultraviolet (EUV) lithography. The process can use EUVL on up to 14 layers (a tangible progress from N7+, which uses EUVL on four non-critical layers) to enable significant improvements in terms of density. TSMC says that when compared to N7 (1st Gen 7 nm, DUV-only), N5 technology will allow chip developers to shrink die area of their designs by ~45%, making transistor density ~1.8x higher. It will also increase frequency by 15% (at the same complexity and power) or reduce power consumption by 20% power reduction (at the same frequency and complexity).

Advertised PPA Improvements of New Process Technologies
Data announced by companies during conference calls, press briefings and in press releases
 TSMC
16FF+
vs
20SOC
10FF
vs
16FF+
7FF
vs
16FF+
7FF
vs
10FF
7FF+
vs
7FF
5FF
vs
7FF
Power60%40%60%<40%10%20%
Performance40%20%30%?same (?)15%
Area Reductionnone>50%70%>37%~17%45%

TSMC finished development of N5 some time ago and its alpha customers with access to pre-production tools are already risk producing chips using the technology. Meanwhile, TSMC has finalized its 5 nm design rule manual (DRM), process design kits (PDKs), and SPICE (simulation program with integrated circuit emphasis) model for those clients who prefer to work with a stable version of design infrastructure.

Besides TSMC’s tools, chip developers can also use a comprehensive set of EDA (electronic design automation) tools from ANSYS, Cadence, Mentor Graphics, and Synopsys. TSMC says that EDA programs from the said companies fully support N5 DRM to ensure necessary accuracy, routability for optimized power, and other aspects of the technology. Obviously, all the tools have been certified by the contract maker of semiconductors.

Finally, TSMC and its partners have also developeda comprehensive N5 IP portfolio that is currently focused primarily on HPC and mobile SoCs. TSMC’s Foundation IP includes high-density and high-performance sets of standard cell libraries and memory compilers. Meanwhile, the company’s partners offer a variety of IP cores for N5 SoCs, including DDR, LPDDR, MIPI, PCIe, and USB PHYs.

“TSMC’s 5-nanometer technology offers our customers the industry’s most advanced logic process to address the exponentially growing demand for computing power driven by AI and 5G,” said Cliff Hou, Vice President of Research & Development/Technology Development at TSMC. “5-nanometer technology requires deeper design-technology co-optimization. Therefore, we collaborate seamlessly with our ecosystem partners to ensure we deliver silicon-validated IP blocks and EDA tools ready for customer use. As always, we are committed to helping customers achieve first-time silicon success and faster time-to-market.”

All the tools required for development of chips to be made using N5 fabrication technology are available from TSMC and its partners right now.

Related Reading

Source: TSMC

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