Yangtze Memory Unveils Xtacking Architecture for 3D NAND: Up to 3 Gbps I/O

Monday, August 6th, 2018 - Memory, Teknologi

Yangtze Memory Unveils Xtacking Architecture for 3D NAND: Up to 3 Gbps I/O

Yangtze Memory Technologies Co. (YMTC) on Monday unveiled key details regarding its Xtacking architecture that will be used for its upcoming 3D NAND flash memory chips. The company's technology involves building NAND chips using two wafers: one wafer containing actual flash memory cells, which are based on a charge trap architecture, and another wafer featuring CMOS logic.

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Traditionally, makers of NAND flash memory produce memory array as well as NAND logic (address decoding, page buffers, etc.) on one wafer using a single process technology. By contrast, YMTC intends to make their NAND array and NAND logic on two different wafers using different process technologies, and then bond the two wafers together, connecting the memory arrays to the logic by metal vias using one additional process step.

The Xtacking architecture is designed to allow YMTC to get ultra-fast I/O while maximizing the density of their memory arrays. The manufacturer says that its 64-layer 3D NAND chips feature I/O speed of 3 Gbps, which is over two times faster when compared to Samsung’s latest V-NAND chips and about three times faster than mainstream 3D NAND. In addition, by locating the controlling logic beneath the NAND memory array, YMTC says that the Xtacking architecture allows them to maximize ttheir 3D NAND capacity and minimize dimensions of its chips.

On paper, the high I/O performance would allow SSD vendors to make low-capacity SSDs with limited NAND channels without today's performance penalty, offsetting the low parallelism with high transfer rates.

YMTC says that usage of two 300-mm wafers instead of one does not increase production costs significantly, as maximizing their memory density allows them to offset the cost of an additional logic wafer. Behind the scenes, the company uses XMC's fabs to produce both memory and logic. YMTC says that it uses a 180-nm process technology developed by XMC to produce the periphery logic.. Meanwhile, like other makers, YMTC does not disclose lithography node it uses for 3D NAND, but typically these manufacturing technologies are pretty ‘rough’ (~ 50 nm) by today’s standards. Because both wafers are processed using mature fabrication technologies, YMTC does not need a very high mix-and-match overlay precision to bond them together and form interconnect vias.

Makers of memory in general tend to keep their die sizes low in a bid to be more competitive and profitable. When it comes to the usual Gb-per-mm2 metrics in case of planar NAND, a smaller die wins in terms of costs because the costs of the wafer are spread out over more chips (of course, putting all complexities and yield rates aside). It gets trickier with 3D NAND as wafers spend more time in chemical vapor deposition (CVD) machines, hence the number of wafers processed by a fab as well as the costs of wafers themselves are no longer crucially important metrics. Nonetheless, they are important enough for companies like YMTC to maximize its NAND density by placing the controlling logic under the memory array.

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Source: YMTC

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