Rambus Unveils PCIe 5.0 Controller & PHY

Thursday, November 14th, 2019 - Interconnect, Teknologi

Rambus Unveils PCIe 5.0 Controller & PHY Rambus has developed a comprehensive PCIe 5.0 and CXL interface solution for chips built using 7 nm process technologies. The interface is now available for licensing by SoC designers and will enable them to bring PCIe 5.0/CXL-supporting hardware...

Synopsys Demonstrates CLX & CCIX 1.1 over PCIe 5.0: Next-Gen In Action

Friday, October 11th, 2019 - Interconnect, Teknologi

Synopsys Demonstrates CLX & CCIX 1.1 over PCIe 5.0: Next-Gen In Action Synopsys, one of the leading developers of chip development tools and silicon IP, demonstrated its CXL over PCIe 5.0 as well as CCIX 1.1 over PCIe 5.0 solutions at ArmTechCon 2019. The showcase...

Intel Starts to Close Omni-Path: OPA1 Xeon CPUs on EOL, OPA2 Axed

Friday, October 11th, 2019 - Interconnect, Teknologi

Intel Starts to Close Omni-Path: OPA1 Xeon CPUs on EOL, OPA2 Axed Intel this week announced plans to discontinue its 1st Generation Xeon Scalable processors with Omni-Path interconnect a year from now. With no 2nd Generation Xeon Scalable products announced to date supporting the technology...

Gen-Z PHY Specification 1.1 Published: Adds PCIe 5.0, Gen-Z 50G Fabric

Friday, October 4th, 2019 - Interconnect, Teknologi

Gen-Z PHY Specification 1.1 Published: Adds PCIe 5.0, Gen-Z 50G Fabric The Gen-Z Consortium this week released Physical Layer Specification 1.1 for Gen-Z interconnects. The new standard adds enhanced support for PCIe Gen 5 as well as Gen-Z 50G Fabric and Local PHY. The publication...

Arm Joins CXL Consortium

Friday, September 13th, 2019 - Interconnect, Teknologi

Arm Joins CXL Consortium Arm has officially joined the Compute Express Link (CXL) Consortium in a bid to enable its customers to implement the new CPU-to-Device interconnect and contribute to the specification. Arm was among a few major technology companies that was yet to join the CXL...

Hot Chips 31 Live Blogs: Gen-Z Chipset for Exascale Fabric

Tuesday, August 20th, 2019 - Interconnect, Teknologi

Hot Chips 31 Live Blogs: Gen-Z Chipset for Exascale Fabric 06:08PM EDT – That’s a wrap, time for a break. 06:07PM EDT – Using 16FF TSMC CoWoS 06:04PM EDT – Cadet Cluster up to 13 DL-385 06:03PM EDT – Cadet is an early access platform...

AMD Joins CXL Consortium: Playing in All The Interconnects

Friday, July 19th, 2019 - Interconnect, Teknologi

AMD Joins CXL Consortium: Playing in All The Interconnects AMD's CTO, Mark Papermaster, has stated in a Website that AMD has joined the Compute Express Link (CXL) Consortium. The industry group is led by nine industry giants including Intel, Alibaba, Google, and Microsoft, but has over...